The foundations of neuromorphic computing

Neuromorphic hardware does best where data arrive as sparse events and power is scarce: sensing, always-on detection, control. On dense arithmetic it has not displaced conventional processors, and most systems remain research platforms. Comparing the two fairly — same task, same accuracy, energy measured end to end — is itself an open problem.

A synapse in a brain changes using only what it can sense locally. One such rule is spike-timing-dependent plasticity: Henry Markram and colleagues showed in 1997 that the relative timing of two neurons’ spikes decides whether the connection between them strengthens or weakens. Chips that learn on-device implement rules of this kind.

A conventional processor spends much of its time and energy moving data to and from memory — the “von Neumann bottleneck”, named by John Backus in 1977. In a brain the synapse both stores the weight and applies it. Neuromorphic designs place memory inside each core, or compute within the memory array itself.

A conventional chip does something on every tick of a global clock. A neuromorphic chip acts only when a spike arrives, and is otherwise idle. Spikes travel as small packets carrying the address of the neuron that fired — the address-event representation developed in Carver Mead’s laboratory around 1990.

Neurons communicate in brief, identical pulses; the information is in which neuron fires and when. The simplest model, the leaky integrate-and-fire neuron, goes back to Louis Lapicque in 1907: input accumulates, leaks away, and triggers a spike on reaching a threshold. Because most neurons are silent most of the time, activity — and energy use — is sparse.

Some eighty-six billion neurons compute on about twenty watts, using slow, unreliable parts. Carver Mead argued in 1990 that the advantage lies in the organising principles rather than the materials, and that electronics could adopt those principles. He called the approach neuromorphic.